AT24C02C [Preliminary]
4. Bus Timing
Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O®
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5. Write Cycle Timing
Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O
SCL
ACK
SDA
8th BIT
WORDn
(1)
wr
t
START
STOP
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
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