93LC76/86
FIGURE 3-1: SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
TCKH
TCKL
VIL
TCSH
VIH
CLK
DI
TDIH
VIL
TDIS
VIH
VIL
TCZ
TPD
TPD
VOH
DO
(Read)
VOL
VOH
VOL
TCZ
TSV
DO
(Program)
STATUS VALID
The memory automatically cycles to the next register.
FIGURE 3-2: READ
TCSL
CS
CLK
...
1
1
0
A
A
0
DI
N
HIGH IMPEDANCE
...
...
0
D
D
D
D
0
DO
N
0
N
FIGURE 3-3: EWEN
TCSL
CS
CLK
...
DI
1
0
0
1
1
X
X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
FIGURE 3-4: EWDS
TCSL
CS
CLK
DI
...
X
1
0
0
0
0
X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’S
1996 Microchip Technology Inc.
Preliminary
DS21131C-page 7