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93LC86C-I/SN 参数 Datasheet PDF下载

93LC86C-I/SN图片预览
型号: 93LC86C-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 1K - 16K与Microwire兼容串行EEPROM [1K-16K Microwire Compatible Serial EEPROMs]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 38 页 / 703 K
品牌: MICROCHIP [ MICROCHIP ]
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93XX46X/56X/66X/76X/86X  
The DO pin indicates the Ready/Busy status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL).  
3.9  
WRITE ALL (WRAL)  
The Write All (WRAL) instruction will write the entire  
memory array with the data specified in the command.  
For 93AAXX and 93LCXX devices, after the last data  
bit is clocked into DI, the falling edge of CS initiates the  
self-timed auto-erase and programming cycle. For  
93CXX devices, the self-timed auto-erase and pro-  
gramming cycle is initiated by the rising edge of CLK on  
the last data bit. Clocking of the CLK pin is not neces-  
sary after the device has entered the WRAL cycle. The  
WRAL command does include an automatic ERAL  
cycle for the device. Therefore, the WRAL instruction  
does not require an ERALinstruction, but the chip must  
be in the EWEN status.  
VCC must be 4.5V for proper operation of WRAL.  
Note:  
For devices with PE functionality such as  
the 93XX76C or 93XX86C, the write  
sequence requires a logic high signal on  
the PE pin prior to the rising edge of clock  
on the last data bit.  
Note:  
After the Write All cycle is complete,  
issuing a Start bit and then taking CS low  
will clear the Ready/Busy status from DO.  
FIGURE 3-10:  
WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES  
TCSL  
CS  
CLK  
0
0
1
X
1
0
•••  
Dx  
•••  
x
D0  
DI  
TSV  
TCZ  
High-Z  
Busy  
DO  
Ready  
HIGH-Z  
TWL  
VCC must be 4.5V for proper operation of WRAL.  
FIGURE 3-11:  
WRAL TIMING FOR 93CXX DEVICES  
TCSL  
CS  
CLK  
0
0
1
X
1
0
•••  
Dx  
•••  
DI  
x
D0  
TSV  
TCZ  
High-Z  
Busy  
DO  
Ready  
HIGH-Z  
TWL  
DS21929D-page 16  
© 2007 Microchip Technology Inc.