93XX46X/56X/66X/76X/86X
3.4
ERASE
The
ERASE
instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93CXX’ devices where
the rising edge of CLK before the last address bit
initiates the write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 3-1:
ERASE TIMING FOR 93AAXX AND 93LCXX DEVICES
T
CSL
CS
Check Status
CLK
DI
High-Z
1
1
1
A
N
A
N
-1 A
N
-2
•••
A0
T
SV
DO
B
USY
T
WC
Ready
T
CZ
High-Z
FIGURE 3-2:
ERASE TIMING FOR 93CXX DEVICES
T
CSL
CS
Check Status
CLK
DI
High-Z
1
1
1
A
N
A
N
-1 A
N
-2
•••
A0
T
SV
DO
Busy
T
WC
Ready
T
CZ
High-Z
©
2007 Microchip Technology Inc.
DS21929D-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
