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93LC86-I/SN 参数 Datasheet PDF下载

93LC86-I/SN图片预览
型号: 93LC86-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8K / 16K 2.5V Microwire串行EEPROM [8K/16K 2.5V Microwire Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 22 页 / 330 K
品牌: MICROCHIP [ MICROCHIP ]
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93LC76/86  
3.4  
Erase All (ERAL)  
3.0  
3.1  
DEVICE OPERATION  
READ  
The ERAL instruction will erase the entire memory array  
to the logical “1” state. The ERAL cycle is identical to  
the erase cycle except for the different opcode. The  
ERAL cycle is completely self-timed and commences  
on the rising edge of the last address bit (A0). Note that  
the Least Significant 8 or 9 address bits are “don’t care”  
bits, depending on selection of x16 or x8 mode. Clock-  
ing of the CLK pin is not necessary after the device has  
entered the self clocking mode. The ERAL instruction is  
ensured at VCC = +4.5V to +6.0V.  
The READ instruction outputs the serial data of the  
addressed memory location on the DO pin. A dummy  
zero bit precedes the 16-bit (x16 organization) or 8-bit  
(x8 organization) output string. The output data bits will  
toggle on the rising edge of the CLK and are stable  
after the specified time delay (TPD). Sequential read is  
possible when CS is held high and clock transitions  
continue. The memory address pointer will  
automatically increment and output data sequentially.  
The DO pin indicates the Ready/Busy status of the  
device if the CS is high. The Ready/Busy status will be  
displayed on the DO pin until the next Start bit is  
received as long as CS is high. Bringing the CS low will  
place the device in Standby mode and cause the DO  
pin to enter the high-impedance state. DO at logical “0”  
indicates that programming is still in progress. DO at  
logical “1” indicates that the entire device has been  
erased and is ready for another instruction.  
3.2  
ERASE  
The ERASE instruction forces all data bits of the  
specified address to the logical “1” state. The self-timed  
programming cycle is initiated on the rising edge of  
CLK as the last address bit (A0) is clocked in. At this  
point, the CLK, CS and DI inputs become “don’t cares”.  
The DO pin indicates the Ready/Busy status of the  
device if the CS is high. The Ready/Busy status will be  
displayed on the DO pin until the next Start bit is  
received as long as CS is high. Bringing the CS low will  
place the device in Standby mode and cause the DO  
pin to enter the high-impedance state. DO at logical “0”  
indicates that programming is still in progress. DO at  
logical “1” indicates that the register at the specified  
address has been erased and the device is ready for  
another instruction.  
The ERAL cycle takes 15 ms maximum (8 ms typical).  
3.5  
Write All (WRAL)  
The WRAL instruction will write the entire memory array  
with the data specified in the command. The WRAL  
cycle is completely self-timed and commences on the  
rising edge of the last address bit (A0). Note that the  
Least Significant 8 or 9 address bits are “don’t cares”,  
depending on selection of x16 or x8 mode. Clocking of  
the CLK pin is not necessary after the device has  
entered the self clocking mode. The WRAL command  
does include an automatic ERAL cycle for the device.  
Therefore, the WRAL instruction does not require an  
ERAL instruction but the chip must be in the EWEN  
status. The WRAL instruction is ensured at Vcc = +4.5V  
to +6.0V.  
The erase cycle takes 3 ms per word (typical).  
3.3  
WRITE  
The WRITE instruction is followed by 16 bits (or by 8  
bits) of data to be written into the specified address.  
The self-timed programming cycle is initiated on the  
rising edge of CLK as the last data bit (D0) is clocked  
in. At this point, the CLK, CS and DI inputs become  
“don’t cares”.  
The DO pin indicates the Ready/Busy status of the  
device if the CS is high. The Ready/Busy status will be  
displayed on the DO pin until the next Start bit is  
received as long as CS is high. Bringing the CS low will  
place the device in Standby mode and cause the DO  
pin to enter the high-impedance state. DO at logical “0”  
indicates that programming is still in progress. DO at  
logical “1” indicates that the entire device has been  
written and is ready for another instruction.  
The DO pin indicates the Ready/Busy status of the  
device if the CS is high. The Ready/Busy status will be  
displayed on the DO pin until the next Start bit is  
received as long as CS is high. Bringing the CS low will  
place the device in Standby mode and cause the DO  
pin to enter the high-impedance state. DO at logical “0”  
indicates that programming is still in progress. DO at  
logical “1” indicates that the register at the specified  
address has been written and the device is ready for  
another instruction.  
The WRAL cycle takes 30 ms maximum (16 ms  
typical).  
The write cycle takes 3 ms per word (typical).  
2004 Microchip Technology Inc.  
Preliminary  
DS21131E-page 7