Using the 93LC56 and 93LC66
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
000A
000C
000D
000E
0010
0011
0012
0013
0015
0016
eeprom equ
0ah
; bit buffer
addr
equ
0ch
; address register
datai
equ
0dh
; stored data input reg.
datao
equ
0eh
; stored data output reg.
txbuf
equ
10h
; transmit buffer
count
equ
11h
; bits transmitted so far
bits
equ
12h
; bits to transmit
bytcnt equ
13h
; byte counter for write routine
loops
equ
15h
; delay loop counter
loops2 equ
16h
; delay loop counter
;************************************************************
;
Bit Assignments
;************************************************************
di
equ
7
; eeprom input
do
equ
6
; eeprom output
datout equ
7
; data out line (port_b)
datin
equ
6
; data in line (port_b)
sclk
equ
5
; clock line (port_b)
chpsel equ
4
; chip select line (port_b)
timeout equ
1
; write cycle timeout warning (port_a)
;
;*************************************************************
org
01ffh
begin
goto
PWRUP
; set the reset vector
org
000h
goto
PWRUP
;
;*************************************************************
;
DATA POLL DELAY ROUTINE
;
This routine delays 100 us is
;
used for delay between polls
;*************************************************************
dpdelay
;
movlw
.25
; timing adjustment variable
movwf
loops2
top
nop
decfsz loops2
; loops complete?
goto
top
; no, go again
;
retlw
0
; yes, return from sub
;
Mon Jun 06 10:49:00 1994
Page 3
0007
0006
0007
0006
0005
0004
0001
01FF
0000
0000
0A26
0000
0A26
0001
0002
0003
0004
0005
0006
0C19
0036
0000
02F6
0A03
0800
16c5x/7x Cross-Assembler V4.12 Released
Line
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
PC
Opcode
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
04C6
0486
04A6
0000
0586
05C6
0000
05A6
0000
0000
04A6
0800
;**************************************************************
;
Start Bit Subroutine
;
this routine generates a start bit
;
(Chip select and DI high when clock goes high)
;**************************************************************;
BSTART
bcf
port_b,datin
; set datain and chipselect lines
bcf
port_b,chpsel ; low just to check operation
bcf
port_b,sclk
; make sure clock starts low too.
nop
;
bsf
port_b,chpsel ; set chip select line high
bsf
port_b,datin
; set data in line high
nop
bsf
port_b,sclk
; set the clock line high to
; generate the start bit
nop
nop
bcf
port_b,sclk
; set clock low again
retlw
0
;
;*************************************************************
DS00560D-page 12
© 1994 Microchip Technology Inc.
8-110
MICROCHIP [ MICROCHIP TECHNOLOGY ]
