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93LC56B-I/SN 参数 Datasheet PDF下载

93LC56B-I/SN图片预览
型号: 93LC56B-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 2K 2.5V微波串行EEPROM [2K 2.5V Microwave Serial EEPROM]
分类和应用: 存储内存集成电路微波光电二极管PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 12 页 / 163 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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93LC56A/B
3.4
ERASE
3.5
Erase All (ERAL)
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2:
CS
ERASE TIMING
T
CSL
CHECK STATUS
CLK
DI
1
1
1
A
N
A
N
-1
A
N
-2
•••
A0
T
SV
T
CZ
READY
HIGH-Z
T
WC
DO
HIGH-Z
BUSY
FIGURE 3-3:
CS
ERAL TIMING
T
CSL
CHECK STATUS
CLK
DI
1
0
0
1
0
X
•••
X
T
SV
T
CZ
READY
HIGH-Z
T
EC
DO
HIGH-Z
BUSY
Guaranteed at Vcc = 4.5V to +6.0V.
©
1997 Microchip Technology Inc.
Preliminary
DS21208A-page 5