93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
Name
PIN DESCRIPTIONS
SOIC/PDIP/
MSOP/
TSSOP
SOT-23
Rotated SOIC
Function
CS
CLK
DI
1
2
3
4
5
6
5
4
3
4
5
6
7
8
Chip Select
Serial Clock
Data In
3
DO
1
Data Out
Ground
Vss
2
ORG/NC
N/A
Organization / 93XX46C
No internal connection / 93XX46A/B
NC
7
8
N/A
6
1
2
No Internal Connection
Power Supply
VCC
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new Start
condition to be detected.
3.1
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
3.2
Serial Clock (CLK)
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum Chip Select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
The Status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
3.5
Organization (ORG)
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
93XX46A devices are always x8 organization and
93XX46B devices are always x16 organization.
2003 Microchip Technology Inc.
DS21749D-page 11
MICROCHIP [ MICROCHIP ]
