欢迎访问ic37.com |
会员登录 免费注册
发布采购

93C56 参数 Datasheet PDF下载

93C56图片预览
型号: 93C56
PDF下载: 下载PDF文件 查看货源
内容描述: 2K 5.0V汽车温度Microwire串行EEPROM [2K 5.0V Automotive Temperature Microwire Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 12 页 / 169 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
 浏览型号93C56的Datasheet PDF文件第1页浏览型号93C56的Datasheet PDF文件第2页浏览型号93C56的Datasheet PDF文件第3页浏览型号93C56的Datasheet PDF文件第4页浏览型号93C56的Datasheet PDF文件第6页浏览型号93C56的Datasheet PDF文件第7页浏览型号93C56的Datasheet PDF文件第8页浏览型号93C56的Datasheet PDF文件第9页  
93C56A/B
3.4
ERASE
3.5
Erase All (ERAL)
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle, except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the rising clock edge of the last address bit.
Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2:
CS
ERASE TIMING
T
CSL
CHECK STATUS
CLK
DI
1
1
1
A
N
A
N
-1
A
N
-2
•••
A0
T
SV
T
CZ
READY
HIGH-Z
T
WC
DO
HIGH-Z
BUSY
FIGURE 3-3:
CS
ERAL TIMING
T
CSL
CHECK STATUS
CLK
DI
1
0
0
1
0
X
•••
X
T
SV
T
CZ
READY
HIGH-Z
T
EC
DO
HIGH-Z
BUSY
©
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 5