93XX46X/56X/66X/76X/86X
3.3
Data Protection
3.0
FUNCTIONAL DESCRIPTION
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AAXX’ and ‘93LCXX’
devices or 3.8V for ‘93CXX’ devices.
When the ORG pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the
DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a High-Z state except when
reading data from the device, or when checking the
Ready/Busy status during a programming operation.
The Ready/Busy status can be verified during an
Erase/Write operation by polling the DO pin; DO low
indicates that programming is still in progress, while
DO high indicates the device is ready. DO will enter
the High-Z state on the falling edge of CS.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS command
should be performed after every write
operation and an external 10 kΩ pull-down
protection resistor should be added to the
CS pin.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWENinstruction must be
performed before the initial ERASEor WRITEinstruction
can be executed.
3.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Note:
To prevent accidental writes to the array in
the 93XX76C/86C devices, set the PE pin
to a logic low.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
Block Diagram
VCC
VSS
HV Generator
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
X
EEPROM
Array
Memory
Control
Logic
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
I/O Control
Logic
Dec
Byte Latches
3.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
Y Decoder
DI
DO
CS
Sense Amp.
R/W Control
CLK
ORG
(1)
(2)
PE
Note 1: ORG pin: Only on 93XX46C/56C/66C/76C/86C.
2: PE pin: Only on 93XX76C/86C.
DS21929D-page 10
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
