25AA320/25LC320/25C320
3.6
Write Status Register Instruction
(WRSR)
When the chip is hardware write-protected, only writes
to nonvolatile bits in the STATUS register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-7 for the WRSR timing sequence.
The Write Status Register instruction (WRSR) allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the STATUS
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two,
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the pro-
grammable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
TABLE 3-2:
BP1
ARRAY PROTECTION
BP0
Array Addresses
Write-Protected
none
upper 1/4
(0C00h-0FFFh)
upper 1/2
(0800h-0FFFh)
all
(0000h-0FFFh)
0
0
1
1
0
1
0
1
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE
CS
0
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction
SI
0
0
0
0
0
0
0
1
7
6
Data to STATUS Register
5
4
3
2
1
0
High-Impedance
SO
©
2008 Microchip Technology Inc.
DS21227F-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
