24LC21A
FIGURE 3-3:
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
®
Display Power-on
or
DDC Circuit Powered
from +5 volts
The 24LC21A was designed to
comply to the portion of flowchart inside dash box
Communication
is idle
Is Vsync
present?
Yes
Send EDID continuously
using Vsync as clock
No
High-to-Low
transition on
SCL?
Yes
No
High-to-Low
transition on
SCL?
Yes
Stop sending EDID.
Switch to DDC2™ mode.
No
DDC2 communication
idle. Display waiting for
address byte.
No
DDC2B
address
received?
Yes
Display has
optional
transition state
?
Yes
Set Vsync counter = 0
or start timer
No
Reset counter or timer
Receive DDC2B
command
No
Change on
SCL, SDA or
VCLK lines?
Yes
No
High-Low
transition on SCL
?
Yes
Reset Vsync counter = 0
Is display
Access.bus
TM
capable?
Yes
Valid Access.bus
address?
Yes
Yes
No
Respond to DDC2B
command
No
Valid
DDC2 address
received?
No
No
VCLK
cycle?
Yes
Increment VCLK counter
(if appropriate)
See Access.bus
specification to determine
correct procedure.
No
Counter=128 or
timer expired?
Yes
Switch back to DDC1™
mode.
Note 1:
The base flowchart is copyright
©
1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2:
The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3:
Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
DS21160G-page 6
©
2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
