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24LC01BT-I/OT 参数 Datasheet PDF下载

24LC01BT-I/OT图片预览
型号: 24LC01BT-I/OT
PDF下载: 下载PDF文件 查看货源
内容描述: 1K I2C ™串行EEPROM [1K I2C™ Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 34 页 / 585 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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24AA01/24LC01B
1K I
2
C
Serial EEPROM
Device Selection Table
Part
Number
24AA01
24LC01B
Note 1:
V
CC
Range
1.7-5.5
2.5-5.5
Max. Clock
Frequency
400 kHz
(1)
400 kHz
Temp.
Ranges
I
I, E
Description:
The Microchip Technology Inc. 24AA01/24LC01B
(24XX01*) is a 1 Kbit Electrically Erasable PROM. The
device is organized as one block of 128 x 8-bit memory
with a 2-wire serial interface. Low-voltage design
permits operation down to 1.7V with standby and active
currents of only 1
μA
and 1 mA, respectively. The
24XX01 also has a page write capability for up to 8
bytes of data. The 24XX01 is available in the standard
8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN,
2x3 TDFN and MSOP packages, and is also available
in the 5-lead SOT-23 and SC-70 packages.
100 kHz for V
CC
<2.5V.
Features:
• Single Supply with Operation down to 1.7V for
24AAXX Devices, 2.5V for 24LCXX Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1
μA,
max. (I-temp)
• 2-Wire Serial Interface, I
2
C™ Compatible
• Schmitt Trigger inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• Page Write Time 3 ms, typical
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programmable Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP, 5-lead SOT-23 and SC-70
• Pb-free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
SOT-23/SC-70
SCL
Vss
SDA
Note:
1
2
3
4
Vcc
5
WP
A0 1
A1 2
A2 3
V
SS
4
V
CC
WP
SCL
A0
A1
A2
SOIC, TSSOP
1
2
3
4
DFN/TDFN
8 V
CC
7 WP
6 SCL
5 SDA
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
Pins A0, A1 and A2 are not used by the 24XX01 (no
internal connections).
Block Diagram
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
©
2009 Microchip Technology Inc.
DS21711J-page 1