25C080/160
FIGURE 3-4:
CS
0
SCK
instruction
SI
0
0
0
0
0
0
1
16 bit address
0 15 14 13 12
2
1
0
7
6
5
data byte 1
4
3
2
1
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
PAGE WRITE SEQUENCE
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2
SI
7
6
5
4
3
2
1
0
7
6
data byte 3
5
4
3
2
1
0
7
data byte n (16 max)
6
5
4
3
2
1
0
FIGURE 3-5:
CS
READ STATUS REGISTER SEQUENCE
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
instruction
SI
0
0
0
0
0
1
0
1
data from status register
6 5
4 3 2 1
high impedance
SO
7
0
FIGURE 3-6:
CS
WRITE STATUS REGISTER SEQUENCE
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
instruction
SI
0
0
0
0
0
0
0
1
7
6
data to status register
5
4
3
2
1
0
high impedance
SO
©
1996 Microchip Technology Inc.
Preliminary
DS21147F-page 9