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24C16 参数 Datasheet PDF下载

24C16图片预览
型号: 24C16
PDF下载: 下载PDF文件 查看货源
内容描述: 8K / 16K 5.0V SPI总线串行EEPROM [8K/16K 5.0V SPI Bus Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 12 页 / 88 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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25C080/160
8K/16K 5.0V SPI
Bus Serial EEPROM
FEATURES
SPI modes 0,0 and 1,1
3 MHz Clock Rate
Single 5V supply
Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1
µ
A typical
Organization
- 1024 x 8 for 25C080
- 2048 x 8 for 25C160
16 Byte Page
Self-timed ERASE and WRITE Cycles
Sequential Read
Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
High Reliability
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
8-pin PDIP/SOIC Packages
Temperature ranges supported
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I):
-40
°
C to +85
°
C
- Automotive (E):
-40˚C to +125˚C
PACKAGE TYPES
PDIP
CS
SO
WP
V
SS
1
25C080/160
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
SOIC
CS
SO
WP
V
SS
1
25C080/160
8
7
6
5
V
CC
HOLD
SCK
SI
2
3
4
BLOCK DIAGRAM
Status
Register
HV Generator
DESCRIPTION
The Microchip Technology Inc. 25C080/160 are 8K and
16K bit Serial Electrically Erasable PROMs. The mem-
ory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a chip select (CS) input, allowing any number
of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP).
WP
SI
SO
CS
SCK
HOLD
Sense Amp.
R/W Control
Y Decoder
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
Array
Vcc
Vss
SPI is a trademark of Motorola.
©
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21147F-page 1