PIC16F818/819
REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode.
I2C mode:
This bit must be maintained clear.
bit 6
CKE: SPI Clock Edge Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON<4>).
I2C mode:
This bit must be maintained clear.
bit 5
D/A: Data/Address bit (I2C mode only)
In I2C Slave mode:
1= Indicates that the last byte received was data
0= Indicates that the last byte received was address
bit 4
bit 3
bit 2
P: Stop bit(1) (I2C mode only)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1) (I2C mode only)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
R/W: Read/Write Information bit (I2C mode only)
Holds the R/W bit information following the last address match and is only valid from address
match to the next Start bit, Stop bit or ACK bit.
1= Read
0= Write
bit 1
bit 0
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (In I2C mode only):
1= Transmit in progress, SSPBUF is full (8 bits)
0= Transmit complete, SSPBUF is empty
Note 1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 72
2004 Microchip Technology Inc.