PIC16F818/819
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ‘b’ in register ‘f’ = 0, the next
The contents of register ‘f’ are
cleared and the Z bit is set.
instruction is executed.
If bit ‘b’ = 1, then the next
instruction is discarded and a NOP
is executed instead, making this a
2 TCY instruction.
BTFSC
Bit Test, Skip if Clear
CLRW
Clear W
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] CLRW
None
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ‘b’ in register ‘f’ = 1, the next
W register is cleared. Zero bit (Z)
is set.
instruction is executed.
If bit ‘b’ in register ‘f’ = 0, the next
instruction is discarded and a NOP
is executed instead, making this a
2 TCY instruction.
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(PC) + 1 → TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits<10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two-cycle instruction.
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
DS39598E-page 106
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
