PIC12CE67X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Words:
Cycles:
Example
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
1(2)
=
0x5A
HERE
FALSE
TRUE
BTFSS FLAG,1
=
=
0x00
1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRW
None
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → (W)
1 → Z
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
0001
0000
0011
10
0kkk
kkkk
kkkk
W register is cleared. Zero bit (Z) is
set.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two cycle instruction.
Description:
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
2
Before Instruction
W
=
0x5A
After Instruction
HERE
CALL THERE
W
=
0x00
1
Before Instruction
Z
=
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
DS40181B-page 66
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
