PIC12C5XX
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
6.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data bus
GP2/T0CKI
Pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
Programmable
Prescaler(2)
PSout
Sync
(2 TCY delay)
T0SE
3
PS2, PS1, PS0(1)
PSA(1)
T0CS(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
1999 Microchip Technology Inc.
DS40139E-page 25
MICROCHIP [ MICROCHIP ]
