PIC12C5XX
FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM
12
8
GPIO
Data Bus
Program Counter
ROM/EPROM
GP0
GP1
512 x 12 or
1024 x 12
RAM
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
Program
STACK1
Memory
25 x 8 or
STACK2
File
Registers
Program
12
RAM Addr
Bus
9
Addr MUX
Instruction reg
Indirect
Addr
5
16 X 8
EEPROM
Data
Memory
PIC12CE5XX
Only
Direct Addr
5-7
FSR reg
STATUS reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2
W reg
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS40139E-page 10
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
