PIC12C5XX
TABLE 8-3:
RESET CONDITIONS FOR REGISTERS
MCLR Reset
WDT time-out
Register
Address
Power-on Reset
Wake-up on Pin Change
(1)
(1)
—
—
W (PIC12C508/509)
qqqq xxxx
qqqq uuuu
(1)
(1)
W (PIC12C508A/509A/
PIC12CE518/519/
PIC12CE509A)
qqqq qqxx
qqqq qquu
INDF
TMR0
PC
00h
01h
02h
03h
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
uuuu uuuu
uuuu uuuu
1111 1111
(2,3)
STATUS
q00q quuu
FSR (PIC12C508/
PIC12C508A/
04h
111x xxxx
111u uuuu
PIC12CE518)
FSR (PIC12C509/
PIC12C509A/
04h
110x xxxx
11uu uuuu
PIC12CE519/
PIC12CR509A)
OSCCAL
(PIC12C508/509)
05h
05h
0111 ----
1000 00--
uuuu ----
uuuu uu--
OSCCAL
(PIC12C508A/509A/
PIC12CE518/512/
PIC12CR509A)
GPIO
06h
06h
--xx xxxx
--uu uuuu
(PIC12C508/PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
GPIO
(PIC12CE518/
PIC12CE519)
11xx xxxx
1111 1111
--11 1111
11uu uuuu
1111 1111
--11 1111
OPTION
TRIS
—
—
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
Note 2: See Table 8-7 for reset value for specific conditions
Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.
TABLE 8-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
MCLR reset during normal operation
MCLR reset during SLEEP
000u uuuu
0001 0uuu
0000 0uuu
0000 uuuu
1001 0uuu
WDT reset during SLEEP
WDT reset normal operation
Wake-up from SLEEP on pin change
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’.
1999 Microchip Technology Inc.
DS40139E-page 39
MICROCHIP [ MICROCHIP ]
