11AAXXX/11LCXXX
3.3
Acknowledge
FIGURE 3-4:
MAK (‘1’)
ACKNOWLEDGE BITS
SAK (‘1’)
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
Note:
A MAK must always be transmitted
following the start header.
The Master Acknowledge, or MAK, is signified by trans-
mitting a ‘
1
’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current operation (and initiate
the write cycle for write operations).
Note:
When a NoMAK is used to end a
WRITE
or
WRSR
instruction, the write cycle is
not initiated if no bytes of data have
been received.
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘
1
’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
Note:
In order to guard against bus contention,
a NoSAK will occur after the start
header.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See Figure 3.3 and Figure 3-4 for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master should then perform a standby pulse and begin
the desired command again.
NoMAK (‘0’)
NoSAK
(1)
Note 1:
A NoSAK is defined as any sequence that is not a
valid SAK.
3.4
Device Addressing
A device address byte is the first byte received from the
master device following the start header. The device
address byte consists of a four-bit family code, for the
11XX this is set as ‘
1010
’. The last four bits of the
device address byte are the device code, which is
hardwired to ‘
0000
’ on the 11XXXX0 devices.
The device code on 11XXXX1 devices is hardwired to
‘0001’. This allows both 11XXXX0 and 11XXXX1
devices to be used on the same bus without address
conflicts.
FIGURE 3-5:
DEVICE ADDRESS BYTE
ALLOCATION
MAK SAK
SLAVE ADDRESS
1
Note 1:
0
1
0
0
0
0
0
(1)
This bit is a ‘1’ on the 11XXXX1.
3.5
Bus Conflict Protection
FIGURE 3-3:
Master
ACKNOWLEDGE
ROUTINE
Slave
To help guard against high current conditions arising
from bus conflicts, the 11XX features a current-limited
output driver. The I
OL
and I
OH
specifications describe
the maximum current that can be sunk or sourced,
respectively, by the SCIO pin. The 11XX will vary the
output driver impedance to ensure that the maximum
current level is not exceeded.
MAK
SAK
DS22067H-page 8
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
