11AAXXX/11LCXXX
4.0
DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. The code for each instruction is listed
in Table 4-1.
TABLE 4-1:
INSTRUCTION SET
Instruction Name Instruction Code Hex Code
Description
READ
CRRD
WRITE
WREN
WRDI
RDSR
WRSR
ERAL
SETAL
0000 0011
0000 0110
0110 1100
1001 0110
1001 0001
0000 0101
0110 1110
0110 1101
0110 0111
0x03
0x06
0x6C
0x96
0x91
0x05
0x6E
0x6D
0x67
Read data from memory array beginning at specified address
Read data from current location in memory array
Write data to memory array beginning at specified address
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read STATUS register
Write STATUS register
Write ‘0x00’ to entire array
Write ‘0xFF’ to entire array
that the slave should output the next data byte. This
continues until the master sends a NoMAK, which ends
the operation.
4.1
Read Instruction
The Read command allows the master to access any
memory location in a random manner. After the READ
instruction has been sent to the slave, the two bytes of
the Word Address are transmitted, with an Acknowl-
edge sequence being performed after each byte. Then,
the slave sends the first data byte to the master. If more
data is to be read, the master sends a MAK, indicating
To provide sequential reads in this manner, the 11XX
contains an internal Address Pointer which is incre-
mented by one after the transmission of each byte. This
Address Pointer allows the entire memory contents to
be serially read during one operation. When the highest
address is reached, the Address Pointer rolls over to
address ‘0x000’ if the master chooses to continue the
operation by providing a MAK.
FIGURE 4-1:
READ COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0(1)
Word Address LSB
Command
Word Address MSB
7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8
SCIO
0 0 0 0 0 0 1 1
Data Byte n
Data Byte 2
Data Byte 1
7 6 5 4 3 2 1 0
SCIO
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Note 1: For the 11XXXX1, this bit must be a ‘1’.
DS22067H-page 10
Preliminary
2010 Microchip Technology Inc.
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