11AA02E48
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 11AA02E48 family of serial EEPROMs support
the UNI/O® protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC® microcon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11AA02E48 devices contain an 8-bit instruction
register. The devices are accessed via the SCIO pin.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period, con-
trols the bus access and initiates all operations, while
the 11AA02E48 works as slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is active.
FIGURE 2-1:
BLOCK DIAGRAM
STATUS
Register
HV Generator
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
Dec
Page Latches
Y Decoder
Current-
Limited
Slope
Control
SCIO
Sense Amp.
R/W Control
VCC
VSS
Note:
This data sheet documents only the
device’s features and specifications that
are in addition to the features and specifi-
cations of the 11AA020 device. For infor-
mation on the features and specifications
shared by the 11AA02E48 and 11AA020
devices, see the “11AAXXX/11LCXXX
Family Data Sheet” (DS22067).
© 2008 Microchip Technology Inc.
Preliminary
DS22122A-page 5
MICROCHIP [ MICROCHIP ]
