11AAXXX/11LCXXX
5.0
DATA PROTECTION
6.0
POWER-ON STATE
The following protection has been implemented to
prevent inadvertent writes to the array:
The 11XX powers on in the following state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset on power-
up
• A Write Enable (WREN) instruction must be issued
to set the write enable latch
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• After a write, ERAL, SETAL, or WRSR command,
the write enable latch is reset
• A low-to-high transition, standby pulse and subse-
quent high-to-low transition on SCIO (the first low
pulse of the header) are required to enter the
active state
• Commands to access the array or write to the
status register are ignored during an internal write
cycle and programming is not affected
.
TABLE 6-1:
WEL
WRITE PROTECT FUNCTIONALITY MATRIX
Protected Blocks
Unprotected Blocks
Status Register
0
1
Protected
Protected
Protected
Writable
Protected
Writable
2010 Microchip Technology Inc.
Preliminary
DS22067H-page 17
MICROCHIP [ MICROCHIP ]
