ML6696
PIN DESCRIPTION
PIN
NAME
(Pin Number in Parentheses is for PLCC Version)
PIN
NAME
FUNCTION
FUNCTION
1 (9)
TXCLK
Transmit clock TTL output. This
25MHz clock is phase-aligned
with the internal 125MHz TX bit
clock. Data appearing at
TXD<3:0> are clocked into the
ML6696 on the rising edge of this
clock.
Receive data TTL output. Output
is valid on RXCLK’s rising edge.
Digital ground
Receive data TTL output. Output
is valid on RXCLK’s rising edge.
Digital positive power supply
16, 17
(20)
DGND3
18 (21) RXDV
Digital ground
Receive data valid TTL output.
This output is high when the
ML6696 is receiving a data
packet. RXDV is valid on RXCLK’s
rising edge.
Digital positive power supply
Receive error TTL output. This
output goes high to indicate error
or invalid symbols within a
packet, or corrupted idle between
packets. RXER is valid on RXCLK’s
rising edge.
MII Serial Management Interface
clock TTL input. A clock at this
pin clocks serial data into or out
of the ML6696’s MII management
registers through the MDIO pin.
The maximum clock frequency at
MDC is 2.5MHz.
MII Serial Management Interface
data TTL input/output. Serial data
are written to and read from the
management registers through this
I/O pin. Input data is sampled on
the rising edge of MDC. Output
data is valid on MDC's rising edge
Digital ground
Digital positive power supply
Digital ground
No connect
Data quantizer offset-correction
loop, offset-storage capacitor input
pin. The capacitor tied between
this pin and AV
CC
stores the
amplified data quantizer offset
voltage and also sets the dominant
pole in the offset-correction loop.
A 0.1µF surface mount is
recommended.
2 (10)
RXD3
19 (22) DV
CC
2
20 (23) RXER
3, 4,
5, (11) DGND1
6 (12)
7 (13)
8 (14)
RXD2
DV
CC
1
RXD1
21 (24) MDC
Receive data TTL output. Output
is valid on RXCLK’s rising edge.
Digital ground
Receive data TTL output. Output
is valid on RXCLK’s rising edge.
Recovered receive clock TTL
output. This 25MHz clock is
phase-aligned with the internal
125MHz bit clock recovered from
the signal received at VIN+/-.
Receive data are clocked out at
RXD<3:0> on the falling edges of
this clock, and should be sampled
on rising edges. RXCLK is phase-
aligned to CLKREF in the absence
of a 100BASE-FX signal at V
IN+/–
.
Carrier Sense TTL output. CRS
goes high in the presence of non-
idle signals at VIN+/-, or when the
ML6696 is transmitting. CRS goes
low when there is no transmit
activity and receive is idle. In
repeater or full-duplex mode, CRS
goes high in the presence of non-
idle signals at V
IN+/–
only.
Collision Detected TTL output.
COL goes high upon detection of
a collision on the network, and
remains high as long as the
collision condition persists. COL is
low when the ML6696 operates in
full-duplex, repeater, or loopback
modes.
22 (25) MDIO
9, 10,
11 (15) DGND2
12 (16) RXD0
13 (17) RXCLK
23 (26) DGND4
24 (27) DV
CC
5
25, 26
(28)
DGND5
27, 28
(29, 30) NC
29 (31) CAPDC
14 (18) CRS
15 (19) COL
3
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
