ML6692
PIN DESCRIPTION
PIN
NAME
(Continued)
FUNCTION
25 (21)
MDIO
MII Management Interface data TTL input/output. Serial data are written to and read
from the ML6692’s management registers through this I/O pin. Input data is sampled on the
rising edge of MDC. Data output should be sampled synchronously with MDC's rising
edge.
Digital ground.
Digital +5V power supply.
Digital ground.
100BASE-T4 enable TTL output. This output goes low if the auto-negotiation function
chooses 100BASE-T4 as the highest common denominator technology. This output is high
on power-up, during auto-negotiation, when the ML6692 enables any other protocol, or
when 100BASE-T4 technology is not supported. If auto-negotiation is disabled, T4EN is
always low.
100BASE-T4 link fail TTL input. When driven high, it indicates a good, 100BASE-T4 link.
When the auto-negotiation function chooses 100BASE-T4 as the highest common
denominator technology, and indicates it by driving T4EN low, T4FAIL should go high
within 750-1000ms; otherwise auto-negotiation is restarted. Driving this pin low after auto-
negotiation is completed, also restarts it. In the parallel detection function, driving this pin
high indicates that the 100BASE-T4 link is ready. If auto-negotiation is disabled and
management register bit 0.13 is set to 1 (100Mb/s data rate selected), driving T4FAIL
high indicates a valid 100BASE-T4 link and disables the ML6692’s 100BASE-TX analog
functions. If bit 13 of the MII Control register is set to 0, T4FAIL has no effect.
Initialization interface mode select and EEPROM interface mode data-in CMOS
input/output. EDIN selects one of three possible interface modes at power up. See table
on page 14 for more detail
Initialization Interface 10BASE-T half duplex CMOS input. When EDIN is high or
floating, this pin has no effect. When EDIN is low, this pin sets the value of bit 11 of the
MII Status register (10Mb/s half duplex), and the default value of bit 5 of the MII
Advertisment register (10BASE-T half duplex capability).
Initialization Interface 10BASE-T full duplex CMOS input/clock CMOS input/output. ECLK
When EDIN is low, this pin sets the value of bit 12 of the MII Status register (10Mb/s full
duplex), and the default value of bit 6 of the MII Advertisement register (10BASE-T full
duplex capability). When EDIN is left floating, this pin provides the output clock to read
initialization data from an external EEPROM. When EDIN is high, this pin is the input
clock to load data from an external microcontroller.
Analog +5V power supply.
Initialization Interface 100BASE-T4 CMOS input and EEPROM or microcontroller
data-out CMOS input. When EDIN is low, this pin sets the value of bit 15 of the MII
Status register (100BASE-T4), and the default value of bit 9 of the MII Advertisement
register (100BASE-T4 capability). When EDIN is floating, this pin is the initialization
data input from an external EEPROM. When EDIN is high, this pin is the initialization
data input from a microcontroller.
Equalizer bias resistor input. An external 9.53k�½, 1% resistor connected between
RGMSET and AGND3 sets internal time constants controlling the receive equalizer
transfer function.
26 (22, 23)
27 (24, 25)
28 (26, 27)
29 (28)
DGND4
DVCC5
DGND5
T4EN
30 (29)
T4FAIL
31 (30)
EDIN
32 (31)
SEL10HD
33 (32)
SEL10FD/
ECLK
34 (33)
35 (34)
AVCC3
SEL100T4/
EDOUT
36 (35)
RGMSET
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
