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ML6673CH 参数 Datasheet PDF下载

ML6673CH图片预览
型号: ML6673CH
PDF下载: 下载PDF文件 查看货源
内容描述: 快速以太网/ FDDI TP- PMD收发器 [Fast Ethernet/FDDI TP-PMD Transceiver]
分类和应用: 以太网
文件页数/大小: 8 页 / 185 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML6673
PIN CONFIGURATION
ML6673
32-Pin PCC (Q32)
RXOUT–
RVCCA
CMREF
TPIN+
RRSET2
TPIN–
N/C
N/C
ML6673
32-Pin TQFP (H32-7)
TGNDA
TVCCA
RGND
N/C
N/C
N/C
4
RXOUT+
RVCCD
SD–
SD+
N/C
TGNDD
LPBK
TXOFF
N/C
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
RRSET1
RRSET2
N/C
N/C
RGND
N/C
N/C
TVCCA
TGNDA
RRSET1
TPIN–
TPIN+
CMREF
N/C
N/C
RVCCA
RXOUT–
1
2
3
4
5
6
7
8
32
31
30
29
28
27
N/C
26
25
24
23
22
21
20
19
18
TPOUT–
TPOUT+
RTSET2
RTSET1
TVCCD
TXIN–
TXIN+
N/C
9
RXOUT+
10
RVCCD
11
SD–
12
SD+
13
N/C
14
TGNDD
15
LPBK
16
TXOFF
17
14 15 16 17 18 19 20
TVCCD
RTSET1
RTSET2
TXIN+
TXIN–
TPOUT+
TPOUT–
PIN DESCRIPTION
NAME
FUNCTION
NAME
FUNCTION
TXIN+, TXIN–
TPOUT+,
TPOUT–
LPBK
TXOFF
RTSET1,
RTSET2
TVCCA,
TVCCD
These differential ECL100K compatible
inputs receive NRZI data from the PHY
for transmission.
Outputs from the NRZI-MLT3 state
machine drive these differential current
outputs. The transmitter filter/transformer
module connects the media to these pins.
This TTL input enables transmitter-
receiver loopback internally when
asserted low. When LPBK is asserted,
signal detect is asserted.
This TTL input forces the NRZI-MLT3
state machine to a high impedence state
when asserted low and shuts off transmit
bias current.
An external 1% resistor connected
between these pins controls the
transmitter output current amplitude.
I
OUT
= 64 x 1.25V/RTSET
Separate analog and digital transmitter
power supply pins help to isolate
sensitive circuitry from noise generating
digital functions. Both supplies are
nominally +5 volts.
TGNDA,
TGNDD
SD+, SD–
TPIN+, TPIN–
RXOUT+,
RXOUT–
RRSET1,
RRSET2
CMREF
RVCCA,
RVCCD
RGND
Analog and digital transmitter grounds
provide separate return paths for clean
and noisy signals.
These differential ECL100K compatible
outputs indicate the presence of a data
signal with an amplitude exceeding a
preset threshold.
MLT-3 encoded data from the receiver
filter/transformer module enters the
receiver through these pins.
Differential ECL100K compatible outputs
provide NRZI encoded data to the PHY.
Internal time constants controlling the
equalizer’s transfer function are set by an
external resistor connected across these
pins.
This pin provides a DC common mode
reference point for the receiver inputs.
Analog and digital supply pins are
separated to isolate clean and noisy
circuit functions. Both supplies are
nominally +5 volts.
Receiver ground.
2