ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
CONTROL
13
14
24
TPOUTOFF#
FOOUTOFF#
PWRDWN#
I (CMOS)
I (CMOS)
I (CMOS)
Active low, the output stage of the twisted pair output is turned off. If not
connected they are pulled high by internal resistors
Active low, the output stage of the fiber optic output is turned off. If not
connected they are pulled high by internal resistors
Active low, all the circuits are powered down. Configuration pins are read and
register bits are initialized 3 to 8µs after a rising edge of PWRDWN#. If not
connected they are pulled high by internal resistors
DATA SIGNAL INPUT/OUTPUT
1
TPOUTP
O
The two operating modes available for these pins are selected with the
configuration pin PECLTP (pin 7) or the configuration bit PECLTP <30.3>
3
TPOUTN
O
Twisted Pair Interface Mode:
Transmit twisted pair positive and complementary outputs. These outputs form
a differential current output pair that drives Multi Level Transition (MLT-3)
waveforms into the network coupling transformer during 100Mbps mode,
Manchester encoded 10Base-T data or Normal Line Pulses (NLPs) during
10Mbps mode, and Fast Link Pulse (FLP) Bursts during Auto-Negotiation.
TPOUTP and TPOUTN must have external pull up resistors to VCC (refer to
description of RTTP pin)
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary outputs. These outputs
form a differential current output pair that drives Non Return to Zero Inverted
(NRZI) encoded 100Base-FX or 100Base-SX symbols during 100Mbps mode,
Manchester encoded 10Base-FL data or OPT_IDL during 10Mbps mode, and
Fiber Link Negotiation Pulse (FLNP) Bursts during Auto-Negotiation. TPOUTP
and TPOUTN must have external pull up resistors to VCC and be AC coupled
to the inputs of a fiber optic PMD module (refer to description of RTTP pin). A
resistor network may be needed to setup the common mode voltage at the
input pins of the PMD module
38
RTTP
I
Twisted pair PECL/LVPECL compatible driver bias resistor. An external resistor
connected between RTTP and ground sets a constant bias current for the
differential output driver circuitryTPOUTP/TPOUTN.
These output currents depend on the operating mode.
The recommended external component values are:
Twisted Pair Mode:
2KΩ, 1%, between RTTP and ground
50Ω, 1%, betweenTPOUTP andVCC
50Ω, 1%, betweenTPOUTN andVCC
PECL Compatible mode:
2KΩ, 1%, between RTTP and ground
62Ω, 1%, betweenTPOUTP andVCC
62Ω, 1%, betweenTPOUTN andVCC
Also AC coupled to the PMD inputs
10
11
TPINP
TPINN
I
I
The two operating modes available for these pins are selected with the
configuration pin PECLTP (Pin 7) or the configuration bit PECLTP <30.3>.
Twisted Pair Interface Mode:
Receive twisted pair positive and complementary inputs. These inputs form a
differential input pair that receives 100Base-TX, FLP Burst, or 10Base-T signal
from the network. The common mode voltage is set internally and the
differential input resistance is about 2KΩ.
The twisted pair interface requires a network consisting of a 1500Pf capacitor
and a 200Ω resistor in parallel; in series with each pin 10 and 11 as shown in
Figure 1.
January 2002
8
PreliminaryDatasheet
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
