ADVANCED
ML6651
PIN DESCRIPTIONS (continued)
Pin # Signal Name
Description
28
GNDFC
GNDQ
GNDB
VCCE
Ground for one PLL, part of the scrambler, fiber optic LED driver, and quantizer.
Ground for the data quantizer and central bias.
34
35
9
Ground for part of the central biasing.
Power supply for the equalizer, one PLL and part of the descrambler and twisted pair driver.
19
23
26
31
16
17
VCCD
VCCL
VCCFC
VCCQ
MDIO
MDC
Power supply for CMOS noisy circuits.
Power supply for the fiber optic LED driver output stage.
Power supply for one PLL, part of the scrambler, fiber optic LED driver, and quantizer.
Power supply for the data quantizer and central bias.
Management data TTL input/output pin.
Management clock TTL input. The maximum frequency can be 12.5MHz instead of the 2.5MHz
limit of IEEE 802.3.
Advanced Datasheet
September 2000
9