ML6599
ABSOLUTE MAXIMUM RATINGS
Signal Line Voltage .................. –0.3 to TERMPWR + 0.3V
Regulator Output Current ......................... –100 to 300mA
TERMPWR Voltage ........................................... –0.3 to 7V
Storage Temperature ................................. –65°C to 150°C
Soldering Temperature ................................ 260°C for 10s
Thermal Impedance (θ
JA
)
SOIC ................................................................ 95°C/W
TSSOP ............................................................ 110°C/W
OPERATING CONDITIONS
TERMPWR Voltage ........................................ 4V to 5.25V
Operating Temperature ................................. 0°C to 70°C
ELECTRICAL CHARACTERISTICS
PARAMETER
Supply
TERMPWR Supply Current
Unless otherwise stated, these specifications apply for 4V
≤
TERMPWR
≤
5.25V, and T
A
= 0°C to 70°C (Note 1)
CONDITIONS
MIN
TYP
MAX
UNITS
L1–L9 = open,
DISCNKT
= open
L1–L9 = 0.2 V,
DISCNKT
= open
DISCNKT
= 0 (active)
4.5
225
75
5.5
250
100
mA
mA
µA
Disconnect Mode Current
DISCNKT
Input Low Voltage
Input High Voltage
Output
Output High Voltage
Output Current
(Normal Mode)
Hot Insertion Peak Current
Output Clamp Level
Sinking Current (per line)
Output Capacitance
(Micro Linear Method)
Output Capacitance
(X3T9.2/855D method)
Regulator
Output Voltage
1.0
TERMPWR – 1.0
V
V
Measuring each signal line
while other eight are high
V
OUT
= 0.2V, Measuring each signal
line while the other eight are high
TERMPWR = 0V, V
REF
= 0V
Any signal line (L1–L9) at 2.85V
I
OUT
= –30mA (Note 2)
V
OUT
= 3.3V (per line)
L1 thru L9,
DISCNKT
= 0
2V
P-P
100kHz square wave
applied biased at 1V D.C.
L1 thru L9,
DISCNKT
= 0
0.4V
P-P
, 1MHz square wave
applied biased at 0.5V D.C.
2.8
20
2.85
2.9
24
V
mA
µA
V
mA
1
–0.15
10
0
12
4
2
0.15
5
pF
6
7
pF
Sourcing 0-200mA
Sinking 0-100mA
2.8
2.8
125
2.85
2.85
150
150
300
1.0
170
2.9
2.9
V
V
mA
mA
mA
Sinking Current
Short Circuit Current
V = 3.5V
V
REF
= 0V
V
REF
= 5V
Dropout Voltage
Thermal Shutdown
Note 1:
L1–L9 = 0.2V
1.2
V
°C
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
3