ML6430/ML6431
GENLOCK PERFORMANCE SPECIFICATIONS
Unless otherwise noted, V = 1 V NTSC test signal for composite inputs, or 100% color bars for component (Note 1).
IN
PP
See Figure 1 for parameter measurement definition
PARAMETER
SYNC SEPARATION
CONDITIONS
MIN
TYP
MAX
UNITS
Min Sync Amplitude
135
mV
V
Max Video Amplitude
3
Clamp timing error
NTC7 AC bounce signal (Note 2)
NTC7 DC bounce signal (Note 3)
10
16
ns
µs
Clamp Recovery TIme
CLOCKRECOVERY
Short Term Output Jitter Rejection
RMS Residual Output Clock Jitter
Peak to Peak (6s), Line to Line Jitter
Head Switch Recovery Time to 1ns Error
Input jitter = 50ns RMS
Input jitter <1ns RMS
Input Jitter < 1ns
–15
600
2.0
4
dB
ps
2.2
15
ns
5µs step H change on or before
line 1
lines
Step Frequency Recovery Time to 1ns Error
1% step H frequency change on or
before line 1
12
ms
Missing Sync Sensitivity
Sync Glitch Sensitivity
4X Clock Duty Cycle
2X Clock Duty Cycle
1X Clock Duty Cycle
Clock Skew — 1X to 2X
Pulse Output Rise Time
Pulse Output Fall Time
Pulse Output Setup Time
Pulse Output Hold Time
(Note 4)
1.0
1.0
ns
ns
%
%
%
ns
ns
ns
ns
ns
(Note 5)
CLOAD = 50pF, fCLK4X < 60MHz
CLOAD = 50pF, fCLK2X < 30MHz
CLOAD = 50pF, fCLK1X < 15MHz
CLOAD = 50pF, fCLK1X < 15MHz
CLOAD = 50pF
40
48
48
60
52
52
6
2
2
10
10
CLOAD = 50pF
CLOAD = 50pF
20
20
CLOAD = 50pF
SERIAL BUS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
Input Impedance fCLK = 100kHz
0
0.8
VCC
1.0
V
V
VCC – 0.8
VIN = 0V
mA
mA
MW
pF
VIN = VCC
D
1.0
1
2
Input Capacitance (CIN
)
SYSTEM TIMING
SCLK Frequency (fCLOCK
Input Hysteresis (VHYS
Spike Suppression (tSPIKE
)
100
kHz
V
)
0.2
10
)
Max length for zero response
VCC Settled to Within 1%
50
ns
Power Setup Time to Valid Data Inputs
ms
6
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
