ML6430/ML6431
SERIAL BUS LOGIC
PARAMETER
SYSTEM TIMING
(Continued)
Wait Time From STOP to START
On S
DATA
(t
WAIT
)
Hold Time for START On S
DATA
(t
HD/START
)
Setup Time for START On S
DATA
(t
SU/START
)
Min LOW Time On S
CLK
(t
LOW
)
Min HIGH Time On S
CLK
(t
HI
)
Hold Time On S
DATA
(t
HD/DATA
)
Setup Time On (t
SU/DATA
)
Fast mode (Note 2)
Slow mode (Note 2)
Rise Time for S
CLK
& S
DATA
(t
LH
)
Fall Time for S
CLK
& S
DATA
(t
HL
)
Setup Time for STOP On S
DATA
(t
SU/STOP
)
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2:
Parameter is Luma dependent.
Note 3:
Reclock time after bounce.
Note 4:
Net phase error for single isolated missing H pulse.
Note 5:
Net phase error for glitch at sync level <50ns.
(Continued)
CONDITIONS
MIN
TYP
MAX
UNITS
1.3
0.6
0.6
1.3
0.6
5.0
100
250
30
30
0.6
300
300
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
COMPOSITE
VIDEO IN
PIN 6
REGENERATED
CSYNC
PIN 26
EQUALIZERS
t
HSW
t
HEQW
SERRATIONS
t
HBLK
t
HBLKW
t
HSTC
SCLAMP
PIN 28
t
HSERRW
HBLANK
PIN 25
t
HSTCW
BGATE
PIN 27
t
HBPC
BCLAMP
PIN 27
t
HBPCW
HRESET
PIN 23
t
HRW
t
HBPGW
NOTE: NOT TO SCALE
Figure 1. Line Rate Waveforms
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
