ML6426
PIN CONFIGURATION
ML6426
16-Pin Narrow SOIC (S16N)
A/B MUX
RINA/YINA
GND
VCC
RINB/YINB
GINA/UINA
GINB/UINB
BINA/VINA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC IN
DISABLE
GNDO
ROUT/YOUT
VCCO
GOUT/UOUT
BOUT/VOUT
BINB/VINB
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
A/B MUX
Logic input pin to select between
Bank <A> and Bank <B> video inputs.
This pin is internally pulled high.
Unfiltered analog R- or Y-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
Analog ground
Analog 5V supply
Unfiltered analog R- or Y-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
8
B
IN
A/V
IN
A Unfiltered analog B- or V-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
B
IN
B/V
IN
B
Unfiltered analog B- or V-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
Analog B or V-channel output
Analog G or U-channel output
5V power supply for output buffers
Analog R or Y-channel output
Analog ground
Disable/Enable pin. Turns the chip off
when logic high. Internally pulled low.
Input for an external H-sync logic
signal for filter channels. CMOS
level input. Active High.
2
R
IN
A/Y
IN
A
9
3
4
5
GND
V
CC
R
IN
B/Y
IN
B
10
11
12
13
14
15
16
B
OUT
G
OUT
V
CCO
R
OUT
GNDO
DISABLE
SYNC IN
6
G
IN
A/U
IN
A Unfiltered analog G- or U-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
G
IN
B/U
IN
B Unfiltered analog G- or U-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
7
2
November, 1999