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ML6423CS-1 参数 Datasheet PDF下载

ML6423CS-1图片预览
型号: ML6423CS-1
PDF下载: 下载PDF文件 查看货源
内容描述: 双S视频低通滤波器的相位和氮化硅/ X均等化 [Dual S-Video Lowpass Filter with Phase and Sinx/x Equalization]
分类和应用: 有源滤波器光电二极管信息通信管理LTE
文件页数/大小: 10 页 / 275 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML6423  
FUNCTIONAL DESCRIPTION  
APPLICATION GUIDELINES  
The ML6423 single-chip dual video filter is intended for  
low cost professional and consumer video applications.  
Each of the two channels incorporates an input buffer  
amplifier, a 6th-order lowpass filter, a 1st-order allpass  
equalizer, sinx/x equalizer and an output 2X gain  
amplifier capable of driving 75W to ground. A third  
output (B) is the sum of the A and C inputs and have the  
identical output amplifier as the A and C channels.  
OUTPUT & INPUT CONSIDERATIONS  
The dual filters have 2X gain. The circuit has 2X gain  
(6dB) when connected to a 150W load, and 0dB gain  
when driving a 75W load via a 75W series output resistor.  
The output may be either AC or DC coupled. For AC  
coupling, the –3dB point should be 5Hz or less. There  
must also be a DC path of £500W to ground for output  
biasing. The ML6423-5 provides higher sink current to  
better drive AC coupled loads.  
The ML6423 can be driven by a DAC with RANGE down  
to 0V. When RANGE is low the input range is 0.5V to  
1.5V. When the input signal range is 0V to 0.1V, RANGE  
should be tied high. In this case, an offset is added to the  
input so that the output swing is kept between 0.5V to  
2.5V. The output amplifier is capable of driving up to  
24mA of peak current; therefore the output voltage should  
not exceed 1.8V when driving 75W to ground.  
The input resistance is 4kW. The input may be either DC  
or AC coupled. (Note that each input sources 80 to 125µA  
of bias current). The ML6423 is designed to be directly  
driven by a DAC. For current output video DACs, a 75W  
or 150W resistor to ground may need to be added to the  
DAC output (filter input).  
SUPPLY NOISE  
CLAMPING  
+5V  
FB2  
+
100  
100Ω  
100µF  
0.1µF  
1nF  
100µF  
1µF  
1µF  
INPUT  
DECOUPLING  
+
2.56kΩ  
V
A
IN  
0.1µF  
85Ω  
2.56kΩ  
1kΩ  
0.1µF  
1
2
16  
15  
V
C
IN  
V
C
V A  
IN  
IN  
+
100µF  
1k  
DC  
BIAS  
INPUT SIGNAL  
= 1V  
P-P  
GND  
RANGE  
GNDA  
85Ω  
INPUT  
TERMINATION  
RESISTOR  
0.1µF  
3
4
14  
13  
1nF  
GNDC  
FB1  
1nF  
0.1µF  
V
V
A
A
CC  
CC  
5
6
7
8
12  
11  
10  
9
NC  
V
V
A
OUT  
OUT  
75Ω  
V
C
OUT  
V
V
V
C
B
NC  
OUT  
75Ω  
75Ω  
0.1µF  
0.1µF  
C
CC  
V
B
CC  
1nF  
V
B
OUT  
1nF  
GNDB  
OUT  
Figure 4. ML6423 AC Coupled DC Bias Test Circuit  
6