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ML6421CS-4 参数 Datasheet PDF下载

ML6421CS-4图片预览
型号: ML6421CS-4
PDF下载: 下载PDF文件 查看货源
内容描述: 三人相和氮化硅/ X均等化,低通滤波器的视频 [Triple Phase and Sinx/x Equalized, Low-Pass Video Filter]
分类和应用: 有源滤波器光电二极管信息通信管理LTE
文件页数/大小: 13 页 / 163 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML6421  
FUNCTIONAL DESCRIPTION  
APPLICATION GUIDELINES  
The ML6421 single-chip Triple Video Filter IC is intended  
for consumer and low cost professional video  
applications. Each of the three channels incorporates an  
input buffer amplifier, a sixth order lowpass filter, a first  
order allpass equalizer, Sinx/x equalizer and an output  
amplifier capable of driving 75to ground.  
OUTPUTCONSIDERATIONS  
The triple filters have unity gain. The circuit has unity  
gain (0dB) when connected to a 150load, and a –6dB  
gain when driving a 75load via a 75series output  
resistor. The output may be either AC or DC coupled. For  
AC coupling, the –3dB point should be 5Hz or less. There  
must also be a DC path of -500to ground for output  
biasing.  
The ML6421 can be driven by a DAC with Range down to  
0V. When Range is low the input and output signal range  
is 0.5V to 2.5V. When the input signal includes 0V, Range  
should be tied high. In this case, an offset is added to the  
input so that the output swing is kept between 0.5V to  
2.5V. The output amplifier is capable of driving up to  
24mA of peak current; therefore the output voltage should  
not exceed 1.8V when driving 75to ground.  
INPUTCONSIDERATIONS  
The input resistance is 4k. The input may be either DC or  
AC coupled. (Note that each input sources 80 to 125µA of  
bias current). The ML6421 is designed to be directly  
driven by a DAC. For current output video DACs, a 75or  
150resistor to ground may need to be added to the DAC  
output (filter input).  
+5V  
FB2  
0.001µF  
SUPPLY NOISE  
CLAMPING  
47Ω  
0.1µF  
100µF  
47Ω  
47Ω  
0.1µF  
1µF  
3.1kΩ  
INB  
1µF  
1µF  
85Ω  
100µF  
INPUT  
DECOUPLING  
0.1µF  
1
16  
15  
14  
13  
12  
11  
10  
9
3.1kΩ  
GNDB  
V
B
A
IN  
1kΩ  
3.1kΩ  
2
INC  
V
IN  
C
V
IN  
100µF  
1kΩ  
DC  
BIAS  
INPUT SIGNAL = 2V  
P-P  
3
1kΩ  
GND  
RANGE  
GNDA  
GND  
85Ω  
0.1µF  
INPUT  
TERMINATION  
4
5
6
7
8
1nF  
1nF  
GNDC  
INA  
FB1  
0.1µF  
0.1µF  
85Ω  
1nF  
100µF  
V
CC  
0.1µF  
V
CC  
C
V
CC  
A
OUTC  
OUTA  
OUTB  
V
C
V
A
OUT  
OUT  
75Ω  
75Ω  
75Ω  
1nF  
V
CC  
B
V
B
OUT  
0.1µF  
Figure 9. ML6421 AC Coupled DC Bias Test Circuit  
8