ML6411
FUNCTIONAL DESCRIPTION
Sync-suppress Gain Control (SGC)
This control function is used for video where the sync
signal is suppressed (i.e., chroma signal). In which case,
the SGC can be activated to provide a 25% gain boost to
each channel (Y and C). The SGC is activated via serial bus
(Register D, Bits D1 and D2), also called the BOOSTA and
BOOSTB programming bits. In the SGC mode, the output
signals are enhanced by amplifying the input signal by the
value of G
SGC
(see Table 5).
Using The Gain Control Blocks Together
The UGC combined provides digital gain control data to a
variable gain control circuit while the SGC is directly in
the A/D processing path. Hence the UGC sets variable
gain control of the A/D.
When the UGC and the SGC are enabled. In this mode,
the output gain is the combination of the different gain
setting mechanisms:
For 1V
P-P
signals,
Equation 1: Output Gain = [<Input Signal> x
G
UGC
x G
SGC
] + Clamp Level
For 2V
P-P
signals,
Equation 2: Output Gain = [<Input Signal> x
G
UGC
x G
SGC
x G
PRESET
] + Clamp Level
Note that separate G
UGC
, G
SGC
, and G
PRESET
values are
available for both channels A and B. There are up to 640
combinations of gain settings possible.
WARNING
Note that it is possible to exceed the output voltage ranges
for standard video using the combination of the gain
setting mechanisms on the input signal. The user should
take precaution in understanding the gain limits necessary
and make the proper selection for each of the gain
mechanism.
A/D CONVERTER
The A/D conversion is performed via a three stage pipeline
architecture. The first two stages quantize their input signal
to the three bits, then subtract the result from the input and
amplify by a factor of four. This creates a residue signal
which spans the full scale range of the following converter.
The subtraction and amplification is performed via a
bottom plate sampling capacitor feedback amplifier,
similar to the input sample and hold. The third stage
quantizes the signal to four bits. One bit from each of the
last two stages is used for error correction.
The first stage A/D performs the conversion at the end of
the sample and holds period, approximately one-half
(Continued)
cycle later, after the subtraction/amplification of the first
stage has settled. The third stage A/D performs the
conversion after another one-half cycle delay, when the
second stage has settled. Error correction is then
performed and, one clock cycle later, data is transferred to
the output latch. This creates a 3 clock latency.
INPUT SAMPLE AND HOLD
The input sample and hold consist of a bottom plate
sampling capacitor feedback amplifier. The input
capacitance is 0.4pF, plus transmission gate. The input to
the sample and hold is driven differentially. The sample
and hold samples the input signal during the positive half
cycle of the input clock, and holds the last value of the
input during the negative half cycle of the input clock. The
settling time of the amplifier is less than 10nS.
INPUT COUPLING AND DC CLAMP PROGRAM
SELECTION
All inputs are AC coupled into the positive sampling
capacitor of the sample and hold. Each input capacitor
becomes the integrating component for the DC restore
clamps. The direction of clamp current depends on the
data at the A/D output during the clamp gating pulse. For
the color channel (i.e. C in Y/C mode) the clamp level is
128. If the code is above this number during the gate
pulse, the current source will sink current from the input
capacitor in order to drive the input voltage lower.
Otherwise, the current source will source current to raise
the input voltage. Clamp currents are shown in Table 6.
The clamp values of 16, 24, 64, 128 can be select via
register program (Register A and B) through the serial bus.
Note that there is no Level 24 in the B channel. The
CLPA<1:0> controls the clamp settings for the
A-channel, while the CLPB<1:0> controls the clamp
settings for the B-channel. For example, clamp values can
be selected independently for the chroma channel in Y/C
mode (CLPB<1:0>). Once the clamp settings are selected,
the clamps are active when the ClampGate is asserted
HIGH. The ClampGate signal is an external signal provided
by a genlock/sync clock device that is genlocked to the
horizontal sync of the video input. The ML6431 can be used
to generate the ClampGate signal (see Application Section).
SERIAL PROGRAM
The ML6411 can be register programmed through the
serial bus. Clamping and gain setting can be selected for
various video formats. This serial bus is a standard three-
pin interface with data, clock, and ground. See Timing
Control information. Table 7 provides a description the
Register information. Please see section “Input Coupling
and DC Clamp Program Selection” and “Gain Select
Control”.
8
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
