ML6401
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
Switching Characteristics
Maximum CLK Input Frequency
Clock Duty Cycle
CONDITIONS
MIN
TYP
MAX
UNITS
20
40
25
25
25
MHz
%
CLK = 13.5MHz
CLK ≤ 20MHz
CLK ≤ 20MHz
60
tPWH
ns
tPWL
ns
Analog To Digital Converter Inputs — CLK
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
Input Capacitance
VIL
0
0.8
VDDD
+5
V
V
VIH
2.4
–5
–5
VIL = 0.1V
VIH = VDDD – 0.1V
µA
µA
pF
+5
4.0
Timing — Digital Outputs (CL = 15pF, IOL = 2mA, RL = 2kΩ, fCLK = 20MHz)
Sampling Delay
tDS
5
ns
ns
ns
ns
ns
Output Hold Time
tHO
tDO
4
5
12
18
10
10
10
30
25
20
Output Delay Time
Three-State Delay Time — Output Enable
Three-State Delay Time — Output Disable
Analog To Digital Converter Outputs — Digital
Low Level Output Voltage
High Level Output Voltage
Output Current in Three-State Mode
Supplies
IOL = 2mA
0
0.6
VCCO
+20
V
V
IOH = 2mA
2.4
–20
µA
Analog, Digital & Output Supply Voltage
Analog Supply Current
4.5
5.5
34
15
10
V
Static
26
10
4
mA
mA
mA
Digital Supply Current
fCLK = 20MHz
fCLK = 20MHz, CL = 0pF
Output Supply Current
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
TIMING DIAGRAM
N+2
N+3
N+1
SAMPLE
(V +) – (V –)
IN
IN
N
N+4
t
DS
CLK
N–3
N–2
N–1
N
N+1
t
t
PWL
PWH
t
t
HO
DO
D0 TO D7
OUT
4
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
