ML6401
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
Switching Characteristics
Maximum CLK Input Frequency
Clock Duty Cycle
t
PWH
t
PWL
Analog To Digital Converter Inputs — CLK
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
Input Capacitance
Timing — Digital Outputs (C
L
= 15pF, I
OL
= 2mA, R
L
= 2kΩ, f
CLK
= 20MHz)
Sampling Delay
Output Hold Time
Output Delay Time
Three-State Delay Time — Output Enable
Three-State Delay Time — Output Disable
Analog To Digital Converter Outputs — Digital
Low Level Output Voltage
High Level Output Voltage
Output Current in Three-State Mode
Supplies
Analog, Digital & Output Supply Voltage
Analog Supply Current
Digital Supply Current
Output Supply Current
Static
f
CLK
= 20MHz
f
CLK
= 20MHz, C
L
= 0pF
4.5
26
10
4
5.5
34
15
10
V
mA
mA
mA
I
OL
= 2mA
I
OH
= 2mA
0
2.4
–20
0.6
VCC
O
+20
V
V
µA
t
DS
t
HO
t
DO
4
5
5
12
18
10
10
10
30
25
20
ns
ns
ns
ns
ns
V
IL
V
IH
V
IL
= 0.1V
V
IH
= VDD
D
– 0.1V
0
2.4
–5
–5
4.0
0.8
VDD
D
+5
+5
V
V
µA
µA
pF
CLK = 13.5MHz
CLK
≤
20MHz
CLK
≤
20MHz
20
40
25
25
25
60
MHz
%
ns
ns
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
TIMING DIAGRAM
SAMPLE
(V
IN
+) – (V
IN
–)
N+1
N+2
N+3
N
N+4
t
DS
CLK
N–3
N–2
t
HO
N–1
N
t
PWH
OUT
N+1
t
PWL
D0 TO D7
t
DO
4
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
