ML5800
PIN
3
SIGNAL
NAME
PAON
I/O
O (CMOS)
FUNCTION
PA Control Output. Enables the off-chip PA at
the correct times in a Transmit slot. Goes high
when transmit RF is present at TXO; goes low
5µs before transmit RF is removed from TXO.
This output has 5mA drivers suitable for
driving pin diode switches directly. It also has
optional interlock logic to disable the PA when
the PLL is out of lock.
DIAGRAM
VDD
31
3
PAON
8
VSS
9
FREF
I (analog)
Input for the 12.288 MHz or 6.144 MHz
reference frequency. This input is used as the
reference frequency for the PLL and as a
calibration frequency for the on-chip filters. An
AC-coupled sine or square wave source drives
this self-biased input. The reference source
must be accurate to 20 PPM.
VCCA
24
9
FREF
40k
40k
8
VSS
11
QPO
O (analog)
Charge Pump Output of the phase detector.
This is connected to the external PLL loop
filter.
VCCPLL
10
11 QPO
8
VSS
15
VTUNE
I (analog)
VCO Tuning Voltage input from the PLL loop
filter. This pin is very sensitive to noise
coupling and leakage currents.
VCCB
13
2.5V
VTUNE
15
3.7k
8
VSS
DS5800-F-02
FINAL DATASHEET
MARCH 2004
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
