ML4880
GATE CLAMP
FUNCTIONAL DESCRIPTION
The gate clamp circuit provides a method of preventing
the buck regulator P-channel MOSFET switches from
accidentally turning on when the input is suddenly
switched to a higher voltage. This condition can occur
during start-up or when an adapter voltage is applied. As
shown in the block diagram, the P DRV drivers are
capacitively coupled to the gates.
The ML4880 converts a 5.5V to 18V input to three outputs
via two synchronous buck controllers and a flyback
controller. The two buck controllers utilize a unique
current mode PFM control architecture that generate
output voltages in the range of 2.5V to 3.5V (output A),
and 4.5V to 5V (output B). The output current is set by
external components, and can exceed 2A on each supply.
The flyback controller also uses a current mode PFM
control scheme and can be used to generate a 6V to 15V
output. Again, the output current of the flyback is
dependent on external components, and output currents
of 500mA are obtainable. Even at light loads, the PFM
architecture maintains high conversion efficiencies over a
wide range of input voltages. If it is necessary to further
extend battery life, the user can shutdown and fully
disconnect each load from the input independently.
Assume that P DRV is in the OFF state, or at V
, and the
REG
gate voltage is held at V through the resistor. The gate-
IN
source voltage of the MOSFET is 0V and the switch stays
off. If a higher input voltage (V + 5V for example) is
IN
suddenly applied with P DRV still in the OFF state, the
source voltage of the MOSFET would jump up to V
+
IN
5V, but the gate would still be at V . The gate-source
IN
voltage becomes –5V and the P-channel MOSFET would
turn on even though P DRV is still in the OFF state. In
order to prevent the MOSFET from turning on, the gate
clamp circuit senses the increase in the input voltage and
pumps charge into the gate side of the coupling capacitor,
quickly charging the capacitor to the new input voltage
level.
BIAS CIRCUITS
The bias circuits are comprised of a linear regulator and a
precision voltage reference. The linear regulator produces
a supply voltage (V
REG
) used by the control circuits. The
REG
V
pin should be bypassed to GND with a 4.7µF to
The CLAMP pin requires a capacitor to GND in order for
the gate clamp circuit to function properly. The capacitor
value should be 1.5 to 2 times the value used for the
coupling capacitor.
10µF capacitor. The precision voltage reference is used by
the feedback circuit of each controller to maintain an
accurate output voltage.
SHUTDOWN LOGIC
BUCK CONTROLLERS
Each controller has a separate shutdown pin. By applying
a logic high to the appropriate pin, the transconductance
amplifier and current comparator of each controller
(shown in Figures 1 and 3) can be disabled. This prevents
switching from occurring and disconnects the load from
the input. All other circuitry within the ML4880 remains
active during shutdown.
A block diagram of the buck controllers is shown in Figure
1. The circuit utilizes a constant ON-time PFM control
architecture. The circuit determines the OFF-time by
waiting for the inductor current to drop to a level set by
the feedback voltage (V ).
FB
V
IN
T
ON
C
L
IN
P DRV
OSCILLATOR/
ONE SHOT
V
OUT
SHOOT THRU
PROTECTION
C
OUT
N DRV
SYNCHRONOUS
RECTIFIER
COMPARATOR
–18mV
R1
+
–
I
SENSE
V
SR
I
L
Rgm
R
SENSE
+
–
V
C
CURRENT
COMPARATOR
TRANSCONDUCTANCE
AMPLIFIER
V
FB
–
+
1.25V
R2
Figure 1. Buck Controller Functional Diagram
4
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
