ML4876
PIN CONFIGURATION
ML4876
20-Pin SSOP (R20)
FEA OUT
FEA–
1
2
20
19
18
17
16
15
14
13
12
11
F ILIM
B OFF
FEA+
3
B ON
L ON
4
GND
VREF
5
L GATE2
HVDD
L GATE1
VDD
ON/OFF
LEA–
6
7
LEA OUT
8
C
9
F GATE
B SYNC OUT
T
L RTD
10
TOP VIEW
PIN DESCRIPTION
PIN NAME
DESCRIPTION
PIN NAME
DESCRIPTION
1
2
3
4
FEA OUT
Output of flyback (contrast) error
amplifier
11
B SYNC OUT Output of MOSFET driver.
Connects to gate of synchronous
FET catch diode.
FEA–
FEA+
L ON
Negative input of flyback
(contrast) error amplifier
12
13
14
F GATE
Connects to gate of MOSFET in
primary side of contrast control
Positive input of flyback (contrast)
error amplifier
VDD
Output of linear regulator. Positive
power for IC.
Logic input. A ”0“ on this pin
disables the lamp driver section
only
L GATE1
Output of MOSFET driver.
Connection to gate of one side of
inverter FET drive pair
5
6
VREF
Voltage reference output
15
16
HVDD
Battery power input to linear
regulator
ON/OFF
Logic input. A ”0“ on this pin
disables the linear regulator
L GATE2
Output of MOSFET driver.
Connection to gate of one side of
inverter FET drive pair
7
LEA–
Negative input for lamp error
amplifier
8
9
LEAOUT
Output of lamp error amplifier
Oscillator timing capacitor
17
18
GND
Ground
C
B ON
Connection to primary side of gate
pulse transformer
T
10 L RTD
Input to resonant threshold detector
19
20
B OFF
F ILIM
Output of MOSFET driver.
Connection to gate of FET that
disables the input power.
Input to current limit comparator
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
