ML4831
AVERAGE CURRENT AND OUTPUT VOLTAGE
REGULATION
TRANSCONDUCTANCE AMPLIFIERS
The PFC voltage feedback, PFC current sense, and the
loop current amplifiers are all implemented as operational
transconductance amplifiers. They are designed to have
low small signal forward transconductance such that a
large value of load resistor (R1) and a low value ceramic
capacitor (<1µF) can be used for AC coupling (C1) in the
frequency compensation network. The compensation
network shown in Figure 2 will introduce a zero and a
pole at:
The PWM regulator in the PFC Control section will act to
offset the positive voltage caused by the multiplier output
by producing an offsetting negative voltage on the current
sense resistor at Pin 4. A cycle-by-cycle current limit is
included to protect the MOSFET from high speed current
transients. When the voltage at Pin 4 goes negative by
more than 1V, the PWM cycle is terminated.
For more information on compensating the average
current and boost voltage error amplifier loops, see
ML4821 data sheet.
1
1
fZ =
fP =
(2)
2π R1C1
2π R1C2
OVERVOLTAGE PROTECTION AND INHIBIT
The OVP pin serves to protect the power circuit from
being subjected to excessive voltages if the load should
change suddenly (lamp removal). A divider from the high
voltage DC bus sets the OVP trip level. When the voltage
on Pin 18 exceeds 2.75V, the PFC transistors are inhibited.
The ballast section will continue to operate. The OVP
threshold should be set to a level where the power
components are safe to operate, but not so low
18
–
2.5V
+
R1
C2
C1
as to interfere with the boost voltage regulation loop.
Figure 2. Compensation Network
LFB OUT
R(SET)
7
6
OSC
+
–
2.5V
R(X)/C(X)
PREHEAT
10
LAMP F.B.
TIMER
5
9
INTERRUPT
+
–
VCC
16
17
UNDER-VOLTAGE
AND THERMAL
SHUTDOWN
V
REF
V
REF
GND
11
2
R(T)/C(T)
IA OUT
8
+
7K
R
–
PFC OUT
OUT A
OUT B
S
15
14
13
12
–V
+
MUL
–
Q
IA +
+
4
PWM (PFC)
7K
–
Q
Q
–1V
+
T
GAIN
MODULATORS
I(SINE)
3
1
EA OUT
P GND
–
EA –/OVP
–
18
2.75V
+
2.5V
+
OVP
Figure 1. ML4831 Block Diagram
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