ML4826
PIN CONFIGURATION
ML4826
20-Pin PDIP (P20)
20-Pin SOIC (S20)
1
2
20
19
18
17
16
IEAO
VEAO
I
V
FB
AC
3
V
REF
I
SENSE
4
V
V
CC2
RMS
5
V
CC1
SS
6
15 PFC OUT
14 PWM 1
V
DC
7
R C
T
T
PWM 2
PGND
AGND
8
13
12
11
RAMP 1
RAMP 2
9
10
DC I
LIMIT
TOP VIEW
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
1
IEAO
PFC transconductance current error
amplifier output
11
12
AGND
PGND
Analog signal ground
Return for the PWM totem-pole
outputs
2
3
I
AC
PFC gain control reference input
I
Current sense input to the PFC current
limit comparator
13
14
15
16
PWM 2
PWM 1
PFC OUT
PWM driver 2 output
PWM drive 1 output
PFC driver output
SENSE
4
5
V
RMS
Input for PFC RMS line voltage
compensation
SS
Connection point for the PWM soft start
capacitor
V
CC2
V
CC1
V
REF
V
FB
Positive supply for the PWM drive
outputs
6
7
V
DC
PWM voltage feedback input
17
18
19
20
Positive supply (connected to an
internal shunt regulator).
R C
Connection for oscillator frequency
setting components
T
T
Buffered output for the internal 7.5V
reference
8
9
RAMP 1
RAMP 2
PFC ramp input
PFC transconductance voltage error
amplifier input
When in current mode, this pin
functions as the current sense input;
when in voltage mode, it is the PWM
input from the PFC output (feedforward
ramp)
VEAO
PFC transconductance voltage error
amplifier output
10
DC I
PWM current limit comparator input
LIMIT
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
