ML4826
FUNCTIONAL DESCRIPTION (Continued)
PFC RAMP (RAMP1)
connected to a separate RC timing network to generate a
voltage ramp against which VDC will be compared. Under
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
The intersection of RAMP1 and the boost current error
amplifier output controls the PFC pulse width. RAMP1 can
be generated in a similar fashion to the R C ramp.
response. As in current mode operation, the DC I
input would be used for output stage overcurrent
protection.
T
T
LIMIT
The current error amplifier maximum output voltage has a
minimum of 6V. The peak value of RAMP1 should not
exceed that voltage. Assuming a maximum voltage of 5V
for RAMP1, Equation 6 describes the RAMP1 time. With a
100kHz PFC frequency, the resistor tied to V , and a
150pF capacitor, Equation 7 solves for the RAMP1 resistor.
No voltage error amplifier is included in the PWM stage of
the ML4826, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP2 input which allows
REF
V
to command a zero percent duty cycle for input
DC
V
REF
– 5V
voltages below 1.5V.
t
= C
×R ×ln
RAMP1
RAMP1
RAMP1
V
REF
(6)
(7)
PWM Current Limit
= 1.1×R
× C
RAMP1
RAMP1
The DC I
pin is a direct input to the cycle-by-cycle
LIMIT
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
10µs
1.1×150pF
t
RAMP1
R
=
=
= 60kΩ
RAMP1
1.1× C
RAMP1
V
IN
OK Comparator
V
REF
The V OK comparator monitors the DC output of the PFC
IN
and inhibits the PWM if this voltage on V is less than its
60kΩ
FB
ML4826
RAMP1
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start commences.
150pF
RAMP2
The RAMP2 input is compared to the feedback voltage
(V ) to set the PWM pulse width. In voltage mode it can
DC
be generated using the same method used for the R C
input. In current mode the primary current sense and
slope compensation are fed into the RAMP2 input.
T
T
Figure 3.
PMW SECTION
Pulse Width Modulator
Peak current mode control with duty cycles greater than
50% requires slope compensation for stability. Figure 4
displays the method used for the required slope
compensation. The example shown adds the slope
compensation signal to the current sense signal.
Alternatively, the slope compensation signal can also be
The PWM section of the ML4826 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4826-1, and at
twice the PFC frequency in the ML4826-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
subtracted form the feedback signal (V ).
DC
In setting up the slope compensation first determine the
down slope in the output inductor current. To determine
the actual signal required at the RAMP2 input, reflect 1/2
of the inductor downslope through the main transformer,
current sense transformer to the ramp input.
Internal to the IC is a 1.5V offset in series with the RAMP2
input. In the example show the positive input to the PWM
converter’s output stage. DC I
, which provides cycle-
LIMIT
by-cycle current limiting, is typically connected to RAMP
2 in such applications. For voltage-mode operation or
certain specialized applications, RAMP2 can be
comparator is developed from V
(7.5V), this limits the
REF
RAMP2 input (current sense and slope compensation) to 6
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
