ML4824
FUNCTIONAL DESCRIPTION (Continued)
No voltage error amplifier is included in the PWM stage
of the ML4824, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
Solving for the minimum value of C :
SS
50µA
CSS = 5ms ´
= 200nF
1.25V
allows V to command a zero percent duty cycle for
Generating V
CC
DC
input voltages below 1.25V.
The ML4824 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power
dissipation while at the same time delivering 10V of gate
drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with a
single resistor in series with the Vcc pin, returned to a bias
supply of typically 18V to 20V. The resistor’s value must be
chosen to meet the operating current requirement of the
ML4824 itself (19mA max) plus the current required by the
two gate driver outputs.
PWM Current Limit
The DC I
pin is a direct input to the cycle-by-cycle
LIMIT
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
V
OK Comparator
IN
The V OK comparator monitors the DC output of the PFC
IN
and inhibits the PWM if this voltage on V is less than its
FB
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start begins.
EXAMPLE:
With a V
of 20V, a V limit of 14.6V (max) and the
CC
BIAS
ML4824 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate
driver current required is:
PWM Control (RAMP 2)
IGATEDRIVE = 100kHz ´ 100nC = 11mA
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
(7)
20V - 14.6V
RBIAS
=
= 180Ω
(8)
19mA + 11mA
To check the maximum dissipation in the ML4824, find
timing components (R
, C
), which will have a
the current at the minimum V (12.4V):
RAMP2
RAMP2
CC
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
20V - 12.4V
ICC
=
= 42.2mA
(9)
180Ω
The maximum allowable I is 55mA, so this is an
CC
Soft Start
acceptable design.
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:
The ML4824 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
50µA
´
1.25V
V
BIAS
CSS = tDELAY
(6)
where C is the required soft start capacitance, and
R
SS
BIAS
t
is the desired start-up delay.
DELAY
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
V
CC
ML4824
GND
10nF
CERAMIC
1µF
CERAMIC
Figure 3. External Component Connections to V
CC
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
