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ML4824CS-1 参数 Datasheet PDF下载

ML4824CS-1图片预览
型号: ML4824CS-1
PDF下载: 下载PDF文件 查看货源
内容描述: 功率因数校正和PWM控制器组合 [Power Factor Correction and PWM Controller Combo]
分类和应用: 功率因数校正光电二极管控制器
文件页数/大小: 16 页 / 267 K
品牌: MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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ML4824  
FUNCTIONAL DESCRIPTION (Continued)  
V
REF  
3) The output of the voltage error amplifier, VEAO. The  
gain modulator responds linearly to variations in this  
voltage.  
The output of the gain modulator is a current signal, in the  
form of a full wave rectified sinusoid at twice the line  
frequency. This current is applied to the virtual-ground  
(negative) input of the current error amplifier. In this way  
the gain modulator forms the reference for the current  
error loop, and ultimately controls the instantaneous  
current draw of the PFC from the power line. The general  
form for the output of the gain modulator is:  
PFC  
OUTPUT  
16  
1
IEAO  
VEAO  
VEA  
V
FB  
IEA  
15  
+
+
2.5V  
AC  
+
I
IAC ´ VEAO  
2
VRMS  
2
4
3
IGAINMOD  
=
´ 1V  
(1)  
GAIN  
MODULATOR  
V
RMS  
I
More exactly, the output current of the gain modulator is  
given by:  
SENSE  
IGAINMOD = K ´ (VEAO - 1.5V) ´ IAC  
Figure 2. Compensation Network Connections for the  
Voltage and Current Error Amplifiers  
-1  
where K is in units of V .  
Note that the output current of the gain modulator is  
limited to 200µA.  
Current Error Amplifier  
Overvoltage Protection  
The current error amplifiers output controls the PFC duty  
cycle to keep the average current through the boost  
inductor a linear function of the line voltage. At the  
inverting input to the current error amplifier, the output  
current of the gain modulator is summed with a current  
which results from a negative voltage being impressed  
The OVP comparator serves to protect the power circuit  
from being subjected to excessive voltages if the load  
should suddenly change. A resistor divider from the high  
voltage DC output of the PFC is fed to V . When the  
FB  
voltage on V exceeds 2.7V, the PFC output driver is shut  
FB  
down. The PWM section will continue to operate. The  
OVP comparator has 125mV of hysteresis, and the PFC  
upon the I  
pin (current into I  
V /3.5k).  
SENSE  
SENSE  
SENSE  
The negative voltage on I  
represents the sum of all  
will not restart until the voltage at V drops below 2.58V.  
SENSE  
FB  
currents flowing in the PFC circuit, and is typically derived  
from a current sense resistor in series with the negative  
terminal of the input bridge rectifier. In higher power  
applications, two current transformers are sometimes used,  
The V should be set at a level where the active and  
FB  
passive external power components and the ML4824 are  
within their safe operating voltages, but not so low as to  
interfere with the boost voltage regulation loop.  
one to monitor the I of the boost MOSFET(s) and one to  
D
monitor the I of the boost diode. As stated above, the  
Error Amplifier Compensation  
F
inverting input of the current error amplifier is a virtual  
ground. Given this fact, and the arrangement of the duty  
cycle modulator polarities internal to the PFC, an increase  
in positive current from the gain modulator will cause the  
output stage to increase its duty cycle until the voltage on  
The PWM loading of the PFC can be modeled as a  
negative resistor; an increase in input voltage to the PWM  
causes a decrease in the input current. This response  
dictates the proper compensation of the two  
transconductance error amplifiers. Figure 2 shows the  
types of compensation networks most commonly used for  
the voltage and current error amplifiers, along with their  
respective return points. The current loop compensation is  
I
is adequately negative to cancel this increased  
SENSE  
current. Similarly, if the gain modulators output decreases,  
the output duty cycle will decrease, to achieve a less  
negative voltage on the I  
pin.  
SENSE  
returned to V to produce a soft-start characteristic on  
REF  
Cycle-By-Cycle Current Limiter  
The I pin, as well as being a part of the current  
feedback loop, is a direct input to the cycle-by-cycle  
current limiter for the PFC section. Should the input  
voltage at this pin ever be more negative than -1V, the  
output of the PFC will be disabled until the protection flip-  
flop is reset by the clock pulse at the start of the next PFC  
power cycle.  
the PFC: as the reference voltage comes up from zero  
volts, it creates a differentiated voltage on IEAO which  
prevents the PFC from immediately demanding a full duty  
cycle on its boost converter.  
SENSE  
There are two major concerns when compensating the  
voltage loop error amplifier; stability and transient  
response. Optimizing interaction between transient  
response and stability requires that the error amplifiers  
8