ML4821
UNDER VOLTAGE LOCKOUT,
OVP AND CURRENT LIMIT
On power-up the ML4821 remains in the UVLO
condition; output low and quiescent current low. The IC
becomes operational when V
CC
reaches 16V. When V
CC
drops below 9V, the UVLO condition is imposed. During
the UVLO condition, the V
REF
pin is “off”, making it
usable as a “flag” for starting up a down-stream PWM
converter.
OVP, SHUTDOWN, AND IC BIAS
When the input to the OVP comparator exceeds V
REF
, the
output of the ML4821 is inhibited. The OVP input also
functions as a “sleep” input, putting the IC into the low
quiescent UVLO state when the OVP pin is pulled below
0.7V.
500
MULTIPLIER OUTPUT CURRENT (µA)
R
T
= 5kΩ
V
RMS
= 3V
400
5.5
–
+
ENABLE
V
REF
4.4V
E/A OUTPUT VOLTAGE
4.5
300
3.5
LOGIC
POWER
V
REF
16
200
2.5
100
1.5
1.0
0
100
200
300
400
500
9V
–
+
0
SINE INPUT CURRENT (µA)
INTERNAL
BIAS
V
CC
15
Figure 7. Gain Modulator Linearity.
Figure 8. Under-Voltage Lockout Block Diagram.
∆V
REF
, REFERENCE VOLTAGE CHANGE (mV)
0
V
CC
= 15V
–4.0
–8.0
–12
T
A
= –55°C
–16
–20
–24
T
A
= 125°C
40
I
CC
SUPPLY CURRENT (mA)
30
20
T
A
= 25°C
10
T
A
= 25°C
0
0
10
20
30
V
CC
SUPPLY VOLTAGE (V)
0
20
40
60
80
100
120
I
REF
, REFERENCE SOURCE CURRENT (mA)
Figure 9. Total Supply Current vs. Supply Voltage.
Figure 10. Reference Load Regulation.
8
Micro Linear
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
