ML4805
FUNCTIONAL DESCRIPTION
1
t
RAMP
(Continued)
V
IN
OK Comparator
The V
IN
OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V
FB
is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
PWM Control (RAMP 2)
operating frequency can typically be approximated by:
f
OSC
=
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
f
OSC
=
100kHz
=
1
t
RAMP
-
5
t
RAMP
=
0.51
´
R
T
´
C
T
=
1
´
10
Solving for R
T
x C
T
yields 2 x 10
-4
. Selecting standard
components values, C
T
= 270pF, and R
T
= 36.5kΩ.
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4805 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device. The PWM is capable of current-
mode or voltage mode operation. In current-mode
applications, the PWM ramp (RAMP 2) is usually derived
directly from a current sensing resistor or current
transformer in the primary of the output stage, and is
thereby representative of the current flowing in the
converter’s output stage. DC I
LIMIT
, which provides
cycle-by-cycle current limiting, is typically connected to
RAMP 2 in such applications. For voltage-mode operation
or certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V
DC
will be compared. Under
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I
LIMIT
input is used for output stage overcurrent protection.
No voltage error amplifier is included in the PWM stage
of the ML4805, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows V
DC
to command a zero percent duty cycle for
input voltages below 1.25V.
PWM Current Limit
The DC I
LIMIT
pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1.5V, the output of the
PWM will be disabled until the output flip-flop is reset by
the clock pulse at the start of the next PWM power cycle.
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R
RAMP2
, C
RAMP2
), which will have a
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
25
µ
A
C
SS
=
t
DELAY
×
(6)
.
125V
where C
SS
is the required soft start capacitance, and
t
DELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of C
SS
:
25
µ
A
=
100nF
C
SS
=
5ms
×
125V
.
In the ML4805, the operating frequency of the PFC
section is fixed at 1/2 of the PWM's operating frequency.
This is done through the use of a 2:1 digital frequency
divider ("T" flip-flop) linking the two functional sections of
the IC.
9
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
