ML4804
FUNCTIONAL DESCRIPTION (Continued)
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
No voltage error amplifier is included in the PWM stage
of the ML4804, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
allows V to command a zero percent duty cycle for
input voltages below 1.25V.
DC
PWM Current Limit
The DC I
pin is a direct input to the cycle-by-cycle
LIMIT
25µA
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
CSS = tDELAY
×
(6)
1.25V
where C is the required soft start capacitance, and
SS
t
is the desired start-up delay.
DELAY
V
OK Comparator
IN
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
The V OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V is less
than its nominal 2.45V. Once this voltage reaches 2.45V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
IN
FB
Solving for the minimum value of C :
SS
25µA
PWM Control (RAMP 2)
CSS = 5ms ×
= 100nF
(6a)
1.25V
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
Generating V
CC
The ML4804 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some
other V regulator, to regulate the voltage supplied to
CC
the part at 15V nominal. This allows low power dissipation
while at the same time delivering 13V nominal gate drive
at the PWM OUT and PFC OUT outputs. If using a Zener
timing components (R
, C
), that will have a
RAMP2
RAMP2
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
DC
C1
RAMP
VEAO
REF
U3
EA
+
–
TIME
DFF
+
–
VSW1
R
D
RAMP
CLK
Q
U1
U2
OSC
U4
Q
CLK
TIME
Figure 4. Typical Trailing Edge Control Scheme
11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
